It is customary during the fabrication of integrated circuits to form various dielectric layers. These dielectric layers provide electric isolation between various portions of an integrated circuit. For example, in the fabrication of an integrated circuit containing field effect transistors (FETs), after the source gate and drain have been formed, a dielectric layer may be deposited to cover the source, gate and drain regions. The dielectric layer provides support for upper levels of metallization, while electrically isolating this metallization from the source, gate and drain.
As integrated circuits geometries continue to shrink, there is a growing desire within the semiconductor industry for processes which form dielectric layers with relatively planar surfaces. Planar dielectrics obviate depth-of-focus problems (which are often encountered when attempting to transfer patterns to non-planar surfaces) and make the formation of multiple levels of overlying metallization easier.
One popular technique for forming a (relatively) planar surface is to form a dielectric, typically by deposition of silicon dioxide from an organometallic precursor gas or from silane. Then the dielectric is etched back (with or without the assistance of an overlying resist material). Experience has shown that the etchback of the relatively conformal silicon dioxide layer produces a resulting dielectric with a comparatively (at least locally) planar surface.
Practical experience in the semiconductor industry has shown that various machines under certain circumstances tend to preferentially etch a dielectric layer in the center of the wafer. Consequently, the dielectric layer covering chips cut from dice located near the center of the wafer may be etched more (and be therefore thinner) than the dielectric layer of chips cut from dice located near the edge of the wafer. This non-uniformity in machine etching makes it difficult to predictably control planarization techniques such as the above-mentioned deposition and etchback technique.
Although the above discussion has been directed toward dielectrics, similar problems may be observed with respect to deposition and etching of metals and polysilicon or amorphous silicon.